40 research outputs found
Advanced Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits
This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed
Linearization of The Timing Analysis and Optimization of Level-Sensitive Circuits
This thesis describes a linear programming (LP) formulation applicable to the static timing analysis of large scale synchronous circuits with level-sensitive latches. The automatic timing analysis procedure presented here is composed of deriving the connectivity information, constructing the LP model and solving the clock period minimization problem of synchronous digital VLSI circuits. In synchronous circuits with level-sensitive latches, operation at a reduced clock period (higher clock frequency) is possible by takingadvantage of both non-zero clock skew scheduling and time borrowing. Clock skew schedulingis performed in order to exploit the benefits of nonidentical clock signal delays on circuit timing. The time borrowing property of level-sensitive circuits permits higher operating frequencies compared to edge-sensitivecircuits. Considering time borrowing in the timing analysis, however, introduces non-linearity in this timing analysis. The modified big M (MBM) method is defined in order to transform the non-linear constraints arising in the problem formulation into solvable linear constraints. Equivalent LP model problemsfor single-phase clock synchronization of the ISCAS'89 benchmark circuits are generated and these problems are solved by the industrial LP solver CPLEX. Through the simultaneous application of time borrowing and clock skew scheduling, up to 63% improvements are demonstrated in minimum clock period with respect to zero-skew edge-sensitive synchronous circuits. The timing constraints governing thelevel-sensitive synchronous circuit operation not only solve the clock period minimization problem but also provide a common framework for the general timing analysis of such circuits. The inclusion of additional constraints into the problem formulation in order to meet the timing requirements imposed by specific applicationenvironments is discussed
A timing optimization method based on clock skew scheduling and partitioning in a parallel computing environment
Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.This paper describes the implementation of a
heuristic method to perform non-zero clock skew scheduling of
digital VLSI circuits in a parallel computing environment. In
the proposed method, circuit partitions that have low number of
timing paths between partitions are formed. Clock skew scheduling
is applied independently to each partition-sequentially or
in parallel on a computing cluster-and results are iteratively
merged. The scalability of the proposed method is superior compared
to conventional non-zero clock skew scheduling techniques
due to the reduction of analyzed circuit sizes (partition sizes) at
each iteration step and the potential to parallelize the analyses
of these partitions. It is demonstrated that after only the first
iteration step of the proposed method, feasible clock schedules
for 65% of the ISCAS'89 benchmark circuits are computed. For
these circuits, average speedups of 2.1X and 2.6X are observed
for sequential and parallel application of clock skew scheduling
to partitions, respectively
Design-for-debug: A vital aspect in education
Paper presented at 2007 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '07, Honolulu, HI.We often assume that debugging is a skill that comes
with common sense. However, we have observed that many
students do not have an inherent aptitude for debugging.
Hands-on projects teaching the engineering design process
can become troublesome for some students who cannot
complete their projects and consequently fail their courses.
In this paper, we advocate the importance of teaching debugging
skills throughout digital design courses, especially
during the introductory courses. We present teaching techniques
in developing the skills for debugging for both introductory
and advanced digital design courses. These techniques
include emphasis on incremental design stages, test
stimuli and observation techniques, and debugging using
critical (divergent and convergent) thinking
Chapter Posidonia oceanica monitoring system on the coast of Aegean Sea of Turkey
Seagrass monitoring is a basic tool for measuring the condition of meadows in parallel to the environmental conditions. Posidonia oceanica meadows are very sensitive to anthropogenic effects. In the present study, two monitoring stations of Posidonia oceanica meadows were established on the Aegean coasts of Turkey in the years 2018 and 2019, at 26 m depth in Ildır Bay (İzmir, Turkey), and at 33 m depth in Kara Ada (İzmir, Turkey). The P. oceanica meadows upper and lower limits were defined by balisage systems. In the laboratory, lepidochronological, morphometric, and phenological parameters were also studied
Timing-driven physical design for VLSI circuits using resonant rotary clocking
Paper presented at the Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico.Resonant clocking technologies are next-generation
clocking technologies that provide low or controllable-skew,
low-jitter and multi-gigahertz frequency clock signals with low
power consumption. This paper describes a collection of circuit
partitioning, placement and synchronization methodologies that
enables the implementation of high speed, low power circuits synchronized
with the resonant rotary clocking technology. Resonant
rotary clocking technology inherently supports (and requires)
non-zero clock skew operation, which permits further improved
circuit performances. The proposed physical design flow entails
integrated circuit partitioning and placement methodologies that
permit the hierarchical application of non-zero clock skew system
timing. This design flow is shown to be a computationally efficient
implementation method
Interconnects for DNA, quantum, in-memory and optical computing: insights from a panel discussion
The computing world is witnessing a proverbial Cambrian explosion of emerging paradigms propelled by applications such as Artificial Intelligence, Big Data, and Cybersecurity. The recent advances in technology to store digital data inside a DNA strand, manipulate quantum bits (qubits), perform logical operations with photons, and perform computations inside memory systems are ushering in the era of emerging paradigms of DNA computing, quantum computing, optical computing, and in-memory computing. In an orthogonal direction, research on interconnect design using advanced electro-optic, wireless, and microfluidic technologies has shown promising solutions to the architectural limitations of traditional von-Neumann computers. In this article, experts present their comments on the role of interconnects in the emerging computing paradigms and discuss the potential use of chiplet-based architectures for the heterogeneous integration of such technologies.This work was supported in part by the US NSF CAREER Grant CNS-1553264 and EU H2020 research and innovation programme under Grant 863337.Peer ReviewedPostprint (author's final draft